Alibaba has unveiled the XuanTie C950 high-performance, 64-bit multi-core CPU IP featuring an out-of-order superscalar microarchitecture, complying with RVA23 profile, and supporting all optional extensions like Vector Crypto, Zacas, and Zama16.
This CPU also supports the proprietary XuanTie AME (Attached Matrix Extension) ISA and can be integrated with Alibaba’s XuanTie TPE (Tensor Processing Engine) IP. The new 64-bit RISC-V core is designed for SoCs with up to eight cores per cluster, aimed at high-performance applications such as cloud computing, edge computing, and AI computing.
XuanTie C950 specifications:
- Architecture – RVA23 Profile
- Up to 8x cores clocked at 3.2 GHz; 22+/GHz Specint2006 base, or a score of around 70 at 3.2 GHz
- Pipeline – Superscalar out-of-order microarchitecture with 8-wide decode
- Floating Point – RISC-V F/D Extension
- Vector – RISC-V Vector Extension v1.0 with Vector Crypto support
- Matrix – XuanTie TPE coprocessor integration (AME v0.5)
- Hypervisor – Suitable for Type #1 and Type #2 hypervisor
- Cache system
- Private L1 and L2 Cache; L2 cache options: 256KB, 512KB, 1024KB, 2048KB, 3072KB
- Optional L3 shared cache: 1MB, 2MB, 3MB, 4MB, or 8MB
- MMU – Sv57/Sv48/Sv39 with PA48
- Bus Architecture
- Direct Connect Mode: CHI.E/CHI.F
- Multi-Processor Mode: AXI4.0/ACE4.0
- Security – CFI (Landing Pad, Shadow Stack)/Smmtt
- QoS
- CBQRI (Capacity and Bandwidth Controller QoS Register Interface)
- Ssqosid (Quality-of-Service Identifiers)
- Interrupt – AIA (Advanced Interrupt Architecture) v1.0
- Debug – RISC-V Debug Specification v1.0.
- Trace – RISC-V Nexus Trace v1.0
- RAS – RERI (RAS Error Record Interface)
- Manufacturing – 5nm process
